In a data processing apparatus, it is often the case that multiple caches are provided. In one such data processing apparatus arrangement there may be, provided a level one cache and a level two cache, both of which may be provided on-chip together with a processor core. A level three memory, which is typically provided off-chip, is a main repository for data values.
Data values required by the processor core are typically stored in the level one cache. The level one cache is rapidly accessible by the processor core. However, in order to maintain rapid access times to the level one cache, its size is typically small. Hence, it is known to provide a level two cache in which data values may be stored on-chip so that they may be accessed should they be required by the processor core without having to perform a slower data access to the level three memory.
Such an arrangement provides for improved performance by enabling the most frequently used data values to be accessible readily by the level one core. But, a problem with such an arrangement is that controlling where to store data values is complicated when more than one cache is provided. Accordingly, it is desired to provide a improved technique for caching data values when more than one cache is provided.